-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  USE WORK.LCSE.all;
  USE WORK.LCSE_test.all;
  
  
  ENTITY tb_topdma_rs_ram IS
  END tb_topdma_rs_ram;

  ARCHITECTURE testbench OF tb_topdma_rs_ram IS 

  -- Component Declaration
  component topdma_rs_ram is
	port(
			Reset    : in  std_logic;-- Asynchronous, active low
			Clk      : in  std_logic;-- System clock, 20 MHz, rising_edge
			RS232_RX : in  std_logic; -- RS232 RX line
			RS232_TX : out std_logic;-- RS232 TX line
			switches : out std_logic_vector(7 downto 0);-- Switch status bargraph
			Temp_L   : out std_logic_vector(6 downto 0);-- Less significant figure of T_STAT
			Temp_H   : out std_logic_vector(6 downto 0);-- Most significant figure of T_STAT
		  -----main control-----------------------------------------
			DMA_ACK   : in  std_logic; --recognition and sharing of buses by the main processor
			Send_comm : in  std_logic; --start of data tx
			DMA_RQ    : out  std_logic; --request for bus to the processor
			READY     : out  std_logic ---=1 when processor is idle, 0-> processor is busy 
			--RX_Empty  :  in  std_logic
		 );
	end component;

   signal Reset      : std_logic;
   signal Clk        : std_logic;
   signal RS232_RX   : std_logic;
   signal RS232_TX   : std_logic;
   signal switches   : std_logic_vector (7 downto 0 );
   signal TEMP_L     : std_logic_vector (6 downto 0 );
   signal TEMP_H     : std_logic_vector (6 downto 0 );
   signal Send_comm  : std_logic;
   signal DMA_RQ     : std_logic;
   signal READY      : std_logic;
   signal DMA_ACK    : std_logic;
  -- signal RX_Empty  	: std_logic;

  BEGIN

  -- Component Instantiation
         UUT : topdma_rs_ram
				port map(	
					Reset      => Reset,
               Clk        => Clk,
               RS232_RX   => RS232_RX,
               RS232_TX   => RS232_TX,
               switches   => switches,
               TEMP_L     => TEMP_L,
               TEMP_H     => TEMP_H,
               Send_comm  => Send_comm,
			      DMA_RQ     => DMA_RQ, 
			      READY      => READY ,
				--	RX_Empty	  =>RX_Empty,
		         DMA_ACK    => DMA_ACK 
					);
  --  Test Bench Statements
  
  Reset <= '0', '1' after 10 ns;
   
clking : PROCESS
   BEGIN
     Clk <= '1', '0' after 25 ns;
     wait for 50 ns;
   END PROCESS;

     tb : PROCESS
     BEGIN
			
			DMA_ACK <=  '0', '1' after 100 us,'0' after 120 us ,'1' after 140 us,'0' after 160 us ,'1' after 180 us;
			RS232_RX <= '1';
			--wait for 10 us;
			--RX_Empty <='1';
			Transmit(RS232_RX, X"0A");
			--wait for 10 us;
			Transmit(RS232_RX, X"55");
			--wait for 10 us;
			Transmit(RS232_RX, X"0B");
			
			Send_comm<='0', '1' after  900 us;
			
        wait for 1000 us; -- will wait forever
     END PROCESS tb;
  --  End Test Bench 

  END testbench;

--configuration CFG_tb_topdma_rs_ram of tb_topdma_rs_ram is
--   for testbench
--   end for;
--end CFG_tb_topdma_rs_ram;